About
State of Practice in Deploying Supercomputers with NVIDIA Superchips (SPIN-NVSC) Workshop will be held during the 55th International Conference on Parallel Processing (ICPP’26), held in Singapore, September 28 - October 1, 2026. SPIN-NVSC is a full day workshop taking place on Monday, September 28.
HPC centres worldwide are navigating a significant architectural transition, as they seek to balance the demands of traditional simulation workloads with the rapid growth of AI and data-intensive applications. The emergence of unified CPU-GPU Superchip platforms — spanning the Grace-Grace, Grace Hopper, Grace Blackwell, and forthcoming Vera Rubin architectures — offers a coherent family of solutions targeting different points in this workload spectrum, from memory-bandwidth-bound simulation to large-scale AI inference and training. With early adopters now deploying these systems into production and Vera Rubin entering availability in the second half of 2026, the community is actively navigating opportunities and challenges spanning system design, software stack integration, workflow portability, application readiness, resiliency, resource management, and energy efficiency. This workshop, organised by the NVIDIA Supercomputing Users Group (NVSUG), brings together HPC practitioners, system architects, and computational scientists deploying or planning to deploy systems based on these architectures. Contributions from application developers and end users are strongly encouraged.
Topics
Key topics include, but are not limited to:
- Architectural considerations and procurement lessons learned
- System integration with existing clusters and storage infrastructure
- Software stack deployment, programming models, and HPC middleware
- Application porting, performance, and tuning for simulation and AI/ML workloads
- Resiliency, resource management, and scheduling for mixed workloads
- Energy efficiency, user education, and community enablement
- Forward-looking perspectives on Vera Rubin deployment and application readiness
Workshop Schedule
The timing of the schedule will be announced when the conference organizers provide information about the coffee/meal breaks. The schedule will include:
- Invited Plenary Talk
- NVSUG Community Update
- NVSUG Panel
- Full Paper Talks (25 minutes)
- Short Paper Talks (15 minutes)
Key Dates
- Submission Deadline:
June 30, 2026July 8, 2026 (AoE) - Notification: July 23, 2026
- Camera Ready Deadline: July 30, 2026 (AoE)
- Workshop: September 28, 2026
Submissions
SPIN-NVSC is accepting short papers (6 pages) and long papers (10 pages). The page limit includes all references and appendices.
SPIN-NVSC workshop uses the ICPP Linklings for submissions.
To submit, please use this link and select the NVSUG submission type. For other submission rules (e.g., blind review rules), please refer to the general ICPP guidelines that the workshop will use.
Committee
Co-Chairs
| Individual | Affiliation |
|---|---|
| Sadaf R. Alam | Bristol Centre for Supercomputing |
| Taisuke Boku | Advanced HPC-AI R&D Support Center |
| Maciej Cytowski | Pawsey Supercomputing Research Centre |
Program Committee
| Individual | Affiliation |
|---|---|
| John Cazes | TACC |
| Brandon Cook | LBNL NERSC |
| Ryohei Kobayashi | Institute of Science Tokyo |
| Adam Lavely | LBNL NERSC |
| Colin McMurtrie | CSCS/ETH Zurich |
| Jorge Luis Galvez Vallejo | National Computational Infrastructure |
| Ugo Varetto | Pawsey Supercomputing Research Centre |
| Wang Yi | NSCC |
| Himeshi De Silva | NSCC |
| Todd Evans | NVIDIA |
| Simon See | NVIDIA |
| Cerlane Leong | CSCS |
Tentative Agenda
Monday, September 28, 2026
| Time | Talk |
|---|---|
| 09:00 – 09:10 | Welcome |
| 09:10 – 10:00 | Keynote Session Chair: Taisuke Boku Surrounding Challenges of GPU-Centric Supercomputing: IO, Energy Efficiency, and Operation, Toshihiro Hanawa, The University of Tokyo |
| 10:00 – 10:30 | NVIDIA Supercomputing User Group (NVSUG) Community Update Colin McMurtrie |
| 10:30 – 11:00 | Break |
| 11:00 – 12:30 | Full Papers Session Session Chair: Colin McMurtrie Portable and Resilient by Design: A Cloud-Style Stack for HPC and AI across NVIDIA Grace and Grace Hopper Superchips, Sadaf R. Alam, Simon McIntosh-Smith Scaling the Extended OpenDwarfs: Evaluating Cross-Vendor CUDA Performance Portability with SCALE, Beau Johnston, Chris Kitching, Matthew Ireland, Michael Søndergaard Characterizing Communication Compression on NVIDIA BlueField-3 DPU for Distributed Training, Taiga Kobayashi, Tomohiro Ueno, Ryohei Kobayashi |
| 12:30 – 13:30 | Lunch |
| 13:30 – 14:40 | Panel Discussion GPU Coding in the AI Era, Moderator: Taisuke Boku, Panelists: Sadaf Alam, Tomohiro Ueno, Toshihiro Hanawa |
| 14:40 – 15:00 | Short Papers Session Session Chair: Ryohei Kobayashi Beyond the HBM Wall: Coherent-Memory Oversubscription for AI Workloads on NVIDIA Grace Hopper, Mohamed Abdelnaby, Wu-chun Feng |
| 15:00 – 15:30 | Break |
| 15:30 – 16:30 | Short Papers Session Session Chair: Colin McMurtrie Grace or Hopper? A Case Study of Wait-Free Concurrent Queues on the NVIDIA Grace Hopper GH200 Superchip, Pratheek Prakash Shetty, Atharva Gondhalekar, Wu-chun Feng Adaptive GPU Sharing for Real-time LLM Serving with Best-effort Workloads, Shuxin Li, Toshihiro Hanawa, Yohei Miki A Preliminary Study on Simultaneous Coscheduling for Discrete GPU vs. Fused GPU, Poorna Gunathilaka, Kirshanthan Sundararajah, Wu-chun Feng |
| 16:30 – 16:45 | Closing Remarks |